1 laser diode driver with apc amplifier for printers ISL58113 the ISL58113 is a high-performan ce laser driver that provides controlled current to grounded laser diodes. a bias current is summed with the switched current at the iout output, allowing the user to optimize laser diode performance. output switched current flows when the lvds signal data is high. the output current returns to the fixed-threshold value when data is low. complete i out shut-off is achieved by holding the chpen low, which will override all other control pins. a fast settling apc amplifier connects directly to the monitor diode. the ISL58113 does not exhibit any time-dependent droop since the calibration gain is stored as a digital number. features ? voltage-controlled ou tput current source ? very few external components needed ? internal lvds termination resistors ? 200mhz switching ?up to 70ma output current ? rise time < 500ps ? fall time < 500ps ? apc loop for write power control ? fast settling apc amplifier ? single +3.3v supply (10%) ? disable feature for power-up protection and conserving power ? zero droop ? pb-free (rohs compliant) load configuration ? common-cathode ld, common-anode pd applications ? laser printer applications ? laser diode current switching ordering information part number (notes 1, 2) part marking package tape & reel (pb-free) pkg. dwg. # ISL58113crz-t13 58113 crz 24 ld qfn l24.4x5b notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pack aged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. iout gnd pdin july 29, 2013 fn7659.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2010, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL58113 2 fn7659.1 july 29, 2013 pin configuration ISL58113 (24 ld qfn) top view 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 thermal nc data datab gnd dis nc nc nc gnd vcc iout vcc vcc pdin gnd nc vc calb hpsb chpen rps rbias rset ivout thermal pad pin descriptions pin name pin number i/o type description data 2 i lvds input data to control laser switching control datab 3 i lvds input data to control laser switching control gnd 4, 18, 24 ground ground dis 5 i digital disable output current nc 1, 6, 7, 19, 23 i no connect no connect chpen 8 i digital chip enable; pull high to enable rps 9 i analog external resistor sets the hsync detection power rbias 10 analog resistors set bias threshold current. see ?applications information? on page 7 for more details rset 11 o analog bandgap derived internal reference ivout 12 o analog calibrate channel with an external trimpot to gnd adjust the iv amplifier gain pdin 13 i analog photo diode input to the iv amplifier vcc 14, 15, 17 power supply voltage iout 16 o analog laser current output hpsb 20 i tll hsync power select enable; active low. during hpsb is low and hsync signal from photo detector is low, the output current is set by rps calb 21 i ttl samples the laser power for apc; active low vc 22 i analog voltage controlling laser switching current; 0v to 2v input for 0% to 100% output thermal pad - exposed thermal pad should be soldered to gnd note: pins with the same name are not necessary internally connec ted together. ldd pins must not be used for connecting together external components or features.
ISL58113 3 fn7659.1 july 29, 2013 important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = +25 c) recommended operating conditions voltages applied to: v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 4.0v all inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc + 0.5v i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc lvds max current inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 3kv charged device model (tested per jesd22-c110d) . . . . . . . . . . . .1.5kv machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd78b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical, notes 3, 4) ja (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 operating ambient temperature range . . . . . . . . . . . . . . . . 0c to +85c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v cc = 3.3v, dis = lo, t a = +25c, r set = 3.0k ? , unless otherwise indicated. parameter description conditions min (note 5) typ max (note 5) unit v cc supply voltage 3.0 3.3 3.6 v isdis supply current (disabled) dis = slpen = hpsb = hi 0.1 1.0 ma is2 supply current (standby) dis = hi 17 22 ma v lo low voltage threshold all ttl inputs 1.2 v v hi high voltage threshold all ttl inputs 2.8 v i lo input low current all ttl inputs -10 -5 a i hi input high current all ttl inputs -1 1 a v shut vcc shut down voltage 2.5 2.8 v v lvds lvds input level differential, with vcm = 1.25v 0.2 v v cmr lvds common mode voltage range 300mv p-p 0.2 2.2 v v c control voltage 0.3 1.45 v r termination internal lvds termination resistor 180
ISL58113 4 fn7659.1 july 29, 2013 laser amplifier output v cc = 3.3v, dis = lo, t a = +25c, r set = 3.0k ? , unless otherwise indicated. parameter description conditions min (note 5) typ max (note 5) unit i out iout sw-max switched output current vc = 1.45v 40 47 ma iout bias-max bias output current r bias = 1k 25 30 ma i off output off current dis pin set to high -75 0 +75 a freq op operating frequency i out = maximum switch current 200 275 mhz iout psrr i out supply sensitivity i out = 20ma, v cc = 3.3v 10% 9 %/v t r-iout i out rise time 10% to 90%; typical ld for printer 0.5 ns t f-iout i out fall time 90% to 10%; typical ld for printer 0.7 ns outenx_t on i out on propagation delay datax crossing to i out at 50% of final value 5 7 ns vc bw bandwidth of vc vc = 1.0v 12 mhz apc electrical specifications v cc = 3.3v, dis = lo, t a = +25c, r set = 3.0k ? , unless otherwise indicated. parameter description conditions min (note 5) typ max (note 5) unit t apc-50 apc response time 0.3v to 1v step of vc 7.5 s ivgain iv amplifier gain external resistor riv = 500 3.1 k note: 5. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested.
ISL58113 5 fn7659.1 july 29, 2013 timing diagram vc i out dis calb data(lvds) hpsb fixed bias level set by r bias off i out rises to its vc defined value using the last calibration gain setting in <1s off chpen set by rps i out control chpen dis data calb hpsb i out comments power-down (sleep mode) 0xxxx off chpen is slow to enable standby (full standby current, no i outs ) 1 1 x x x off full standby current, no i out normal drive 10x11 on, bias only 1 0 x 0 1 on, cal to level set by vc 10111 on hsync power 1 0 x 1 0 hsync power output current defined by rps invalid logic combination 10x1x invalid note: data1 and data2: 1 implies data>datab, 0 implies data ISL58113 6 fn7659.1 july 29, 2013 typical application gnd 0.1f gnd rbias gnd bandgap ref. data datab logic block iv amplifier vc nc chpen nc iout rset laser 0.1f 4.7f 68 +3.3v bead + - + - switching driver vcc vcc + - dis vcc pdin ivout hpsp calb nc gain control cal. pot rps logic cntrl nc nc 3k ? 3k ? 3k ? + -
ISL58113 7 fn7659.1 july 29, 2013 applications information apc system overview as the laser heats up (or ages) its output power declines relative to the applied current, so some form of power control is required. the laser is optically coupled to a photo-diode, so that the laser?s optical output can be measured. laser optical output power is controlled by comparing the exte rnally applied control voltage with the voltage produced by the iv-amplifier which converts the photo-diode?s output current into a voltage. since the calibrated gain is stored as a digital number in a register, the ISL58113 exhibits none of the time-depende nt droop that is seen in most printers' laser diode drivers. this is of particular importance during high dot/inch graphics modes where the line may be slowed down very significantly to allow 2400 dots per inch or even more. fixed-threshold laser bias control when a laser is driven from below threshold to well above threshold, it exhibits a few cycl es of a damped oscillation. the amplitude of this oscillation is minimized when the laser is kept above threshold. the ?fixed? bias mode is set by asserting a logic low on the slpen pin. to set the laser bias threshold currents, i bias , connect external resistors from rbias pins to gnd. figure 1 shows value of r bias corresponding to desired bias current. scaling external resistors r set is used to scale the switch ing output current. switching output current, i sw , is the function of vc and r set . where i sw gain = ~17, r dac = 400 . r bias sets bias threshold current. figure 1 exhibits the relationship between i bias and r bias . the bias current is set as equation 2: where biaschannelgain = ~40, internalvref = 1.0v. controlling the sampling the switching levels are sampled independently. this can be done during the ?off-paper? period. during calibration mode, the intern al servo control will bring the laser diode output power level to match the voltage control level set by vc voltage. horizontal edge detection when hpsb is low, the output current is set by rps. asserting hpsb low overrides both channel data inputs. hpsb should not be asserted low during a calibration cycle. when hpsb is low, the desired output current i rps is governed by the following equation: where the caldac setting (from th e last write power calibration) ensures laser temperature an d aging compensation. the caldac?s units are ohms. full scale is about 380 ? and caldac is defined as caldac = 255/code*380 ? . the horizontal sync pulse is meant to be a power level that overrides vc calibration and sets the output current to a fixed level. typical application upon the printer being powered up, the lasers should be calibrated. this would establish nominal light power outputs, typically a few milliwatts at the laser regardless of the ambient temperature and also any laser aging. once everything is ready for printi ng, the paper is in position and the mirror-motor is phase-locked then the print line(s) can be written. before, or after, the beam is over the photo-sensitive drum, each laser can be re-calibrated. this continual re- calibration will compensate for any temperature drift of the laser, especially at the initial warming up period. since the calibrated gain is stored as a digital number in a register, the ISL58113 exhibits no time-dependent droop. with no droop to degrade performance the only limitation now is the lasers' own temperature change along the line. this in turn can be compensated for to some extent by adding a data-dependent compensation signal to the analog vcx input pin. it may be found that in fast draft modes for exam ple, that the laser temperature change is sufficiently small that many lines can be written before the laser(s) need to be re-calibrated. if the printed page has a low enough duty cycle, no re-calibration may be needed at all. the ISL58113 has analog voltage inputs to allow the laser power level to be adjusted during the line. typically this would be driven with a pwm, low bandwidth signal to compensate for the differing beam path length as th e beam is swept from one side of the page to the other. figure 1. r bias vs bias current 1 10 100 0.1 1 10 r bias (k ) i bias (ma) i sw i sw gain vc r dac --------------- - 2 r set --------------- ? ?? ?? = (eq. 1) i bias biaschannelgain internalvref r bias ----------------------------------- - = (eq. 2) i rps 40 rps caldac ----------------------- 1.05v r set --------------- - = (eq. 3)
ISL58113 8 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7659.1 july 29, 2013 for additional products, see www.intersil.com/en/products.html note on illegal logic combination in normal use, calb going low (active) without dis being low (active) would be meaningless. likewise with hpsb going low (active). therefore, a combination of these sh ould be avoided at all times. if this combination is applied, the chip will not work properly. to exit this mode, either set calb to low or/and dis to hi . power supply decoupling due to the high values of current being switched rapidly on and off, it is important to ensure that the power supply is well decoupled to ground. during switching, the v cc undergoes severe current transients, thus every effo rt should be made to decouple the v cc as close to the package as possible. symptoms that could arise include poor rise/fall times, current overshoot, and poor settling response. it is recommended that vcc inputs should be bypassed with 4.7f // 100nf // 470pf to gnd. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability figure 2. illegal combination calb dis hpsb revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 7/29/13 fn7659.1 conversion to new intersil template. 6/23/10 fn7659.0 initial release.
ISL58113 9 fn7659.1 july 29, 2013 package outline drawing l24.4x5b 24 lead quad flat no-lead plastic package rev 0, 10/06 6 6 0 . 00 min. detail "x" 0 . 05 max. 5 top view pin 1 index area bottom view side view (2.50) (24x0.60) (3.50) typical recommended land pattern 0.10 pin #1 index area chamfer 0.400 x 45 2.50 3.50 24x0.40 0.250.05 see detail x'' 0.50 0.50 4.00 0.5x6=3.00 ref (24x0.25) (20x0.50) 0.5x4=2.00 ref (4.80 typ) (3.80 typ) 0.900.10 5.00 seating plane 0.08 c 0.10 c 0.10 m c a b c b a c 24 20 19 13 1 7 8 12 0 . 20 ref 4x notes: 1. dimensions are in millimeters. dimensions in ( ) for reference only. 2. dimensioning and tolerancing conform to amse y14.5m-1994. 3. unless otherwise specified, tolerance : decimal 0.05 4. dimension b applies to the metallized terminal and is measured between 0.20mm and 0.30mm from the terminal tip. 5. tiebar shown (if present) is a non-functional feature. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 indentifier may be either a mold or mark feature.
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